(1) Field of the Invention
The present invention relates to a chemical mechanical polishing slurry including a fluoride containing additive. This invention is also related to methods for using the chemical mechanical polishing slurry to polish multiple metal layers and thin-films in a single step during the manufacture of integrated circuits and semiconductors.
(2) Description of the Related Art
Integrated circuits are made up of millions of active devices formed in or on a silicon substrate. The active devices, which are initially isolated from one another, are united to form functional circuits and components. The devices are interconnected through the use of well-known multilevel interconnections.
Interconnection structures normally have a first layer of metallization, an interconnection layer, a second level of metallization, and sometimes a third and subsequent level of metallization. Interlevel dielectrics such as doped and undoped silicon dioxide (SiO.sub.2), are used to electrically isolate the different levels of metallization in a silicon substrate or well. The electrical connections between different interconnection levels are made through the use of metallized vias. U.S. Pat. No. 4,789,648, which is incorporated herein by reference, describes a method for preparing multiple metallized layer and metallized vias in insulator films. In a similar manner, metal contacts are used to form electrical connections between interconnection levels and devices formed in a well. The metal vias and contacts are generally filled with tungsten and generally employ an adhesion layer such as titanium nitride (TiN) and/or titanium to adhere a metal layer such as a tungsten metal layer to SiO.sub.2. At the contact level, the adhesion layer acts as a diffusion barrier to prevent tungsten and SiO.sub.2 from reacting.
In one semiconductor manufacturing process, metallized vias or contacts are formed by a blanket tungsten deposition followed by a chemical mechanical polish (CMP) step. In a typical process, via holes are etched through an interlevel dielectric (ILD) to interconnection lines or to a semiconductor substrate. Next, a thin adhesion layer such as titanium nitride and/or titanium is generally formed over the ILD and is directed into the etched via hole. Then, a tungsten film is blanket deposited over the adhesion layer and into the via. The deposition is continued until the via hole is filled with tungsten. Finally, the excess metal is removed by chemical mechanical polishing, (CMP) to form metal vias. Processes for manufacturing and/or CMP of ILD's are disclosed in U.S. Pat. Nos. 4,671,851, 4,910,155 and 4,944,836.
In a typical chemical mechanical polishing process, the substrate is placed in direct contact with a rotating polishing pad. A carrier applies pressure against the backside of the substrate. During the polishing process, the pad and table are rotated while a downward force is maintained against the substrate back. An abrasive and chemically reactive solution, commonly referred to as a "slurry" is deposited onto the pad during polishing. The slurry initiates the polishing process by chemically reacting with the film being polished. The polishing process is facilitated by the rotational movement of the pad relative to the substrate as slurry is provided to the wafer/pad interface. Polishing is continued in this manner until the desired film on the insulator is removed.
The slurry composition is an important factor in the CMP step. Depending on the choice of the oxidizing agent, the abrasive, and other useful additives, the polishing slurry can be tailored to provide effective polishing to metal layers at desired polishing rates while minimizing surface imperfections, defects and corrosion and erosion. Furthermore, the polishing slurry may be used to provide controlled polishing selectivities to other thin-film materials used in current integrated circuit technology such as titanium, titanium nitride and the like.
Typically CMP polishing slurries contain an abrasive material, such as silica or alumina, suspended in an oxidizing, aqueous medium. For example, U.S. Pat. No. 5,244,523 to Yu et al. reports a slurry containing alumina, hydrogen peroxide, and either potassium or ammonium hydroxide that is useful to remove tungsten at predictable rates with little removal of the underlying insulating layer. U.S. Pat. No. 5,209,816 to Yu et al. discloses a slurry comprising perchloric acid, hydrogen peroxide and a solid abrasive material in an aqueous medium. U.S. Pat. No. 5,340,370 to Cadien and Feller discloses a tungsten polishing slurry comprising approximately 0.1M potassium ferricyanide, approximately 5 weight percent silica and potassium acetate. Acetic acid is added to buffer the pH at approximately 3.5.
U.S. Pat. No. 5,340,370 discloses two slurries. The first slurry is useful for polishing tungsten and includes an abrasive and an oxidizing agent such as potassium ferricyanide. The second slurry is useful for polishing titanium and includes a fluoride salt complexing agent and an abrasive. The reference further discloses that detrimental polishing results are obtained when the slurries are combined.
It has been recognized that CMP slurries have low polishing rates towards titanium. As a result, the polishing step is lengthened or operated at aggressive polishing conditions that can cause undesirable erosion of the SiO.sub.2 layer and recessing of the tungsten vias. Such recessing causes a non-planar via layer to be formed which impairs the ability to print high resolution lines during subsequent photolithography steps and can cause the formation of voids or open circuits in the metal interconnections formed above. Additionally, recessing increases when over polishing is used to ensure complete removal of the titanium and tungsten films across the surface of a wafer. Thus, presently available CMP slurries are inadequate to reliably polish a plurality of metal layers including a titanium layer in an integrated circuit. Accordingly, a new CMP polishing slurry that polishes titanium at a higher rate is needed to overcome the present substrate manufacturing reliability issues.